優化絕熱量... 子通量超導電路之分離器和緩衝器插入的快速且有效演算法 (An Efficient and Effective Optimization Algorithm for Buffer and Splitter Insertion in AQFP Circuits)more

優化絕熱量子通量超導電路之分離器和緩衝器插入的快速且有效演算法 (An Efficient and Effective Optimization Algorithm for Buffer and Splitter Insertion in AQFP Circuits)

針對雙面繞... 線且基於邊界框的網表規劃方法 (A Bounding Box-based Net Partitioning Method for Double-sided Routing)more

針對雙面繞線且基於邊界框的網表規劃方法 (A Bounding Box-based Net Partitioning Method for Double-sided Routing)

考慮巨集之... 面對面三維積體電路設計全局放置 (Face-to-Face 3D-IC Design Global Placement With Macro Consideration)more

考慮巨集之面對面三維積體電路設計全局放置 (Face-to-Face 3D-IC Design Global Placement With Macro Consideration)

在考慮巨集... 之下的面對面三維晶片設計分割流程與巨集合法化 (Face-to-Face 3D-IC Design Partitioning Flow With Macro Consideration And Macro Legalization)more

在考慮巨集之下的面對面三維晶片設計分割流程與巨集合法化 (Face-to-Face 3D-IC Design Partitioning Flow With Macro Consideration And Macro Legalization)

面對面三維... 積體電路設計的詳細放置 (Detailed Placement for Face-to-Face 3D-IC Design)more

面對面三維積體電路設計的詳細放置 (Detailed Placement for Face-to-Face 3D-IC Design)

先進混合列... 高設計的細部擺置 (Detailed Placement for Advanced Mixed-Row-Height Designs)more

先進混合列高設計的細部擺置 (Detailed Placement for Advanced Mixed-Row-Height Designs)

基於動態規... 劃法生成非整數倍數混合元件高度設計的列配置 (Dynamic Programming Based Row Configuration Generator for Non-Integer Multiple-Cell-Height Designs)more

基於動態規劃法生成非整數倍數混合元件高度設計的列配置 (Dynamic Programming Based Row Configuration Generator for Non-Integer Multiple-Cell-Height Designs)

考量混合列... 高設計列配置的全局佈局 (Row Configuration Aware Global Placement for Mixed-Row-Height Designs)more

考量混合列高設計列配置的全局佈局 (Row Configuration Aware Global Placement for Mixed-Row-Height Designs)

用於量子電... 路的基於強化學習的量子位元佈局 (Reinforcement Learning Based Qubit Placement for Quantum Circuits)more

用於量子電路的基於強化學習的量子位元佈局 (Reinforcement Learning Based Qubit Placement for Quantum Circuits)

最小化最大... 位移的線性時間混和列高元件合法化演算法 (Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement)more

最小化最大位移的線性時間混和列高元件合法化演算法 (Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement)

生成用於功... 率優化的混合驅動多位元正反器 (Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization)more

生成用於功率優化的混合驅動多位元正反器 (Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization)

藉由多列細... 部擺置最大化電力線段的插置 (Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement)more

藉由多列細部擺置最大化電力線段的插置 (Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement)

用於先進混... 合列高設計的全局佈局器 (A Global Placer for Advanced Mixed-Row-Height Designs)more

用於先進混合列高設計的全局佈局器 (A Global Placer for Advanced Mixed-Row-Height Designs)

應用於單通... 量量子電路且考量時鐘樹的新型擺置演算法 (A Novel Clock Tree Aware Placement Algorithm for Single Flux Quantum Logic Circuits)more

應用於單通量量子電路且考量時鐘樹的新型擺置演算法 (A Novel Clock Tree Aware Placement Algorithm for Single Flux Quantum Logic Circuits)

考慮單元最... 大負載電容的繞線提升技術的2.5D積體電路拆分製造上的雙重安全防禦方法 (A Doubly Secure Defense Approach on 2.5D IC Split Manufacturing considering Cell Max Load Capacitance and Wire Lifting Technique)more

考慮單元最大負載電容的繞線提升技術的2.5D積體電路拆分製造上的雙重安全防禦方法 (A Doubly Secure Defense Approach on 2.5D IC Split Manufacturing considering Cell Max Load Capacitance and Wire Lifting Technique)

一種新型雙... 重保護的分裂製造防禦模型並同時搭配線段提升演算法下的2.5D積體電路設計 (An Innovative Doubly-secure Split Manufacturing Defense Model with Wire Lifting Algorithm for 2.5D IC Technology)more

一種新型雙重保護的分裂製造防禦模型並同時搭配線段提升演算法下的2.5D積體電路設計 (An Innovative Doubly-secure Split Manufacturing Defense Model with Wire Lifting Algorithm for 2.5D IC Technology)

多重2.5... D FPGA 系統的時間導向繞線並同時配置線段分時復用之演算法 (A Timing-Driven Routing Algorithm with Simultaneous TDM Assignment in Multi-2.5D FPGA Systems)more

多重2.5D FPGA 系統的時間導向繞線並同時配置線段分時復用之演算法 (A Timing-Driven Routing Algorithm with Simultaneous TDM Assignment in Multi-2.5D FPGA Systems)

使用混合元... 件庫之設計的布局合法化演算法 (A Legalization Approach for Mixed-Row-Height Designs)more

使用混合元件庫之設計的布局合法化演算法 (A Legalization Approach for Mixed-Row-Height Designs)

在線性時間... 下的元件配置合法化與元件最大位移最佳化 (A Linear-Time Algorithm for Placement Legalization with Optimal Maximum Displacement)more

在線性時間下的元件配置合法化與元件最大位移最佳化 (A Linear-Time Algorithm for Placement Legalization with Optimal Maximum Displacement)

混合高度之... 元件與列之設計擺置合法化 (Placement Legalization for Designs with Mixed-Height Cells and Rows)more

混合高度之元件與列之設計擺置合法化 (Placement Legalization for Designs with Mixed-Height Cells and Rows)

具分時複用... I/O 的多重2.5D FPGA 系統腳位定位最佳化 (Pin Assignment Optimization for Multi-2.5D FPGA-based Systems with Time-Multiplexed I/Os)more

具分時複用 I/O 的多重2.5D FPGA 系統腳位定位最佳化 (Pin Assignment Optimization for Multi-2.5D FPGA-based Systems with Time-Multiplexed I/Os)

考量安全性... 之 2.5D 積體電路封裝分割 (Security-Aware Bipartitioning For 2.5D IC Packaging)more

考量安全性之 2.5D 積體電路封裝分割 (Security-Aware Bipartitioning For 2.5D IC Packaging)

在繞線後階... 段考慮導通孔之可製造性結合引導式自組裝及冗餘導通孔並透過導線擾動和虛擬導通孔輔助之 (Considering Via Manufacturability with Directed Self-Assembly at Post-Routing Stage Using Wire Perturbation and Dummy Via Insertion)more

在繞線後階段考慮導通孔之可製造性結合引導式自組裝及冗餘導通孔並透過導線擾動和虛擬導通孔輔助之 (Considering Via Manufacturability with Directed Self-Assembly at Post-Routing Stage Using Wire Perturbation and Dummy Via Insertion)

考量多元件... 間距限制下的單元件高度細部擺置 (Single-Cell-Height Detailed Placement Considering Multi-Cell Spacing Constraints)more

考量多元件間距限制下的單元件高度細部擺置 (Single-Cell-Height Detailed Placement Considering Multi-Cell Spacing Constraints)

多重2.5... D FPGA系統腳位定位最佳化 (Pin Assignment Optimization for Multi-2.5D FPGA-based Systems)more

多重2.5D FPGA系統腳位定位最佳化 (Pin Assignment Optimization for Multi-2.5D FPGA-based Systems)

在雙列標準... 元件設計中考慮電源線對齊限制的超大型積體電路佈局 (VLSI Placement for Modern Design with Double-Row Height Standard Cells Considering Power Line Alignment Constraint)more

在雙列標準元件設計中考慮電源線對齊限制的超大型積體電路佈局 (VLSI Placement for Modern Design with Double-Row Height Standard Cells Considering Power Line Alignment Constraint)

Perfo... rmance Driven Logic Replication for FPGA Emulation System (針對FPGA仿真系統所做的效能導向邏輯元件複製)more

Performance Driven Logic Replication for FPGA Emulation System (針對FPGA仿真系統所做的效能導向邏輯元件複製)

滿足最小佈... 值區域限制之擺放及臨界電壓調整 (Minimum Implant Area-Aware Placement and Threshold Voltage Refinement)more

滿足最小佈值區域限制之擺放及臨界電壓調整 (Minimum Implant Area-Aware Placement and Threshold Voltage Refinement)

多重排高標... 準元件之擺置合法化 (Mixed-Cell-Height Standard Cell Placement Legalization)more

多重排高標準元件之擺置合法化 (Mixed-Cell-Height Standard Cell Placement Legalization)

結合虛擬導... 通孔及冗餘導通孔的引導式自組裝暨多重圖案法之分解方法 (Optimizing DSA-MP Decomposition and Redundant Via Insertion with Dummy Vias)more

結合虛擬導通孔及冗餘導通孔的引導式自組裝暨多重圖案法之分解方法 (Optimizing DSA-MP Decomposition and Redundant Via Insertion with Dummy Vias)

新穎繞線於... 金屬凸塊製成之技術演進 (A Novel Routing Framework for Technology Migration with Bump Encroachment)more

新穎繞線於金屬凸塊製成之技術演進 (A Novel Routing Framework for Technology Migration with Bump Encroachment)

為了製程遷... 徙的基於隱性連通圖的迷宮繞線 (Implicit Connection Graph Maze Routing for Layout Migration)more

為了製程遷徙的基於隱性連通圖的迷宮繞線 (Implicit Connection Graph Maze Routing for Layout Migration)

考慮密度平... 整限制之虛擬金屬填充 (Dummy Fill Insertion Considering Density Uniformity Constraint)more

考慮密度平整限制之虛擬金屬填充 (Dummy Fill Insertion Considering Density Uniformity Constraint)

三維晶片上... 佈局規劃之線長導向漸進式直通矽晶穿孔再分配 (Wirelength-Driven Incremental TSV Redistribution on 3-D IC Floorplanning)more

三維晶片上佈局規劃之線長導向漸進式直通矽晶穿孔再分配 (Wirelength-Driven Incremental TSV Redistribution on 3-D IC Floorplanning)

考慮元件位... 移限制與密度的細部電路佈局與佈局合理化之演算法 (Density Aware Detailed Placement and Legalization Considering Displacement Constraint)more

考慮元件位移限制與密度的細部電路佈局與佈局合理化之演算法 (Density Aware Detailed Placement and Legalization Considering Displacement Constraint)

針對工程變... 更命令電路利用布林可滿足性問題使邏輯差異最小化 (A SAT-based Minimal Logic Difference Engine for Functional ECO)more

針對工程變更命令電路利用布林可滿足性問題使邏輯差異最小化 (A SAT-based Minimal Logic Difference Engine for Functional ECO)

一個快速平... 行的移除共同路徑悲觀的方法 (A Fast Parallel Approach for Common Path Pessimism Removal)more

一個快速平行的移除共同路徑悲觀的方法 (A Fast Parallel Approach for Common Path Pessimism Removal)

適性邏輯模... 組式可程式化邏輯陣列之線長導向叢集演算法 (A novel Wirelength-Driven Packing Algorithm for FPGAs with Adaptive Logic Modules)more

適性邏輯模組式可程式化邏輯陣列之線長導向叢集演算法 (A novel Wirelength-Driven Packing Algorithm for FPGAs with Adaptive Logic Modules)

一個有效率... 的塊狀基礎統計時序分析方法 (An Efficient Approach to Block-based Statistical Timing Analysis)more

一個有效率的塊狀基礎統計時序分析方法 (An Efficient Approach to Block-based Statistical Timing Analysis)