在多裸晶系... 統中透過身分授權和數據加密增強匯流排通訊安全 (Enhancing BUS Communication Security in Multi-Die Systems by Identity Authorization and Data Encryption)more

在多裸晶系統中透過身分授權和數據加密增強匯流排通訊安全 (Enhancing BUS Communication Security in Multi-Die Systems by Identity Authorization and Data Encryption)

速度適應之... 可重構容錯多核心系統 (Speed Adaptive Reconfigurable Fault-tolerant Multi-Core System)more

速度適應之可重構容錯多核心系統 (Speed Adaptive Reconfigurable Fault-tolerant Multi-Core System)

針對芯粒電... 路中週期基礎連接線使用調整過的脈衝消失測試實現獨立於連接性的內建自我修復 (Connectivity-Independent Built-In Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test)more

針對芯粒電路中週期基礎連接線使用調整過的脈衝消失測試實現獨立於連接性的內建自我修復 (Connectivity-Independent Built-In Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test)

基於鎖存可... 變電容單元優化數位控制震盪器以降低標準細胞元件庫全數位相位鎖定迴路的抖動 (Jitter Minimization for a Cell-Based All-Digital Phase-Locked Loop by Optimization of Digital Controlled Oscillator Using Latch-Based Varactor Cells)more

基於鎖存可變電容單元優化數位控制震盪器以降低標準細胞元件庫全數位相位鎖定迴路的抖動 (Jitter Minimization for a Cell-Based All-Digital Phase-Locked Loop by Optimization of Digital Controlled Oscillator Using Latch-Based Varactor Cells)

基於增強脈... 衝消失測試對三維堆疊動態隨機存取記憶體中矽穿孔的小延遲缺陷檢測與修復 (Test and Repair of Small Delay Defects Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test)more

基於增強脈衝消失測試對三維堆疊動態隨機存取記憶體中矽穿孔的小延遲缺陷檢測與修復 (Test and Repair of Small Delay Defects Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test)

使用交叉查... 核檢測 RISC-V 核心中的特洛伊木馬 (Trojan Horse Detection for RISC-V Cores Using Cross-Auditing)more

使用交叉查核檢測 RISC-V 核心中的特洛伊木馬 (Trojan Horse Detection for RISC-V Cores Using Cross-Auditing)

多相位鎖延... 遲迴路電路中的檢查並平衡校準方法 (A Check-and-Balance Calibration Scheme in Multi-Phase Delay Lock Loop)more

多相位鎖延遲迴路電路中的檢查並平衡校準方法 (A Check-and-Balance Calibration Scheme in Multi-Phase Delay Lock Loop)

基於兩相位... 鎖延遲迴路且可容忍製程電壓溫度變異的倍頻電路並使用循環脈衝縮減時間量化器進行抖動學習 (PVT-Resilient Frequency Doubling Circuit based on Two-Phase DLL using Cyclic TDC-based Jitter Learning)more

基於兩相位鎖延遲迴路且可容忍製程電壓溫度變異的倍頻電路並使用循環脈衝縮減時間量化器進行抖動學習 (PVT-Resilient Frequency Doubling Circuit based on Two-Phase DLL using Cyclic TDC-based Jitter Learning)

一個使用乒... 乓型延遲線且支援寬頻率範圍的高彈性全數位鎖相迴路 (A Highly Resilient ADPLL Using Ping-pong Delay Line Supporting A Wide Frequency Range)more

一個使用乒乓型延遲線且支援寬頻率範圍的高彈性全數位鎖相迴路 (A Highly Resilient ADPLL Using Ping-pong Delay Line Supporting A Wide Frequency Range)

在協作三維... 晶片設計環境下用差模信號實現本地容錯穿矽連接孔 (Localized Fault-Tolerant TSVs using Differential Signaling For Cooperative 3D-IC Design Environment)more

在協作三維晶片設計環境下用差模信號實現本地容錯穿矽連接孔 (Localized Fault-Tolerant TSVs using Differential Signaling For Cooperative 3D-IC Design Environment)

使用三重模... 組冗餘之投票前的同步技術之容錯型鎖相迴路電路設計 (Fault and Soft-Error Tolerant Phase-Locked Loop Using a Synchronization-before-Voting TMR Scheme)more

使用三重模組冗餘之投票前的同步技術之容錯型鎖相迴路電路設計 (Fault and Soft-Error Tolerant Phase-Locked Loop Using a Synchronization-before-Voting TMR Scheme)

高面積效率... 測試時脈產生方法之邏輯電路線上速度分級設計及其老化故障偵測應用 (Built-In Speed-Grading for Logic Circuits with an Area-Efficient Test Clock Generation Scheme and an Application for Ageing Fault Detection)more

高面積效率測試時脈產生方法之邏輯電路線上速度分級設計及其老化故障偵測應用 (Built-In Speed-Grading for Logic Circuits with an Area-Efficient Test Clock Generation Scheme and an Application for Ageing Fault Detection)

一種使用單... 向變容細胞且以標準元件庫細胞為基礎對製程自適應的循環脈衝縮減時間量化器 (A Process-Adaptive Cell-based Cyclic Pulse-Shrinking Time-to-Digital Converter Using One-Way Varactor Cell)more

一種使用單向變容細胞且以標準元件庫細胞為基礎對製程自適應的循環脈衝縮減時間量化器 (A Process-Adaptive Cell-based Cyclic Pulse-Shrinking Time-to-Digital Converter Using One-Way Varactor Cell)

一種支持安... 全關鍵IC產品早期死亡故障篩查的適當壓力測試和基於多壓力水平的壽命預測方法 (A Just-Enough Stress Test Methodology to Support Infant-Mortality Fault Screening and Multi-Stress-Level-Based Lifetime Prediction for Safety-Critical IC Products)more

一種支持安全關鍵IC產品早期死亡故障篩查的適當壓力測試和基於多壓力水平的壽命預測方法 (A Just-Enough Stress Test Methodology to Support Infant-Mortality Fault Screening and Multi-Stress-Level-Based Lifetime Prediction for Safety-Critical IC Products)

支援 IE... EE Std 802.3bs 之性能導向里德- 所羅門編解碼器 RS(544,514)編譯器 (Performance Driven Reed-Solomon RS(544, 514) Codec Compiler supporting IEEE Std 802.3bs)more

支援 IEEE Std 802.3bs 之性能導向里德- 所羅門編解碼器 RS(544,514)編譯器 (Performance Driven Reed-Solomon RS(544, 514) Codec Compiler supporting IEEE Std 802.3bs)

以變換電壓... 之下的抖動量測量為基礎的鎖相迴路嚴格測試方法 (Rigorous Test Flow for PLL using Jitter Measurement with VDD Sweeping)more

以變換電壓之下的抖動量測量為基礎的鎖相迴路嚴格測試方法 (Rigorous Test Flow for PLL using Jitter Measurement with VDD Sweeping)

具有製程適... 應能力以及支援從容退化之線上失效監控技術之容錯型鎖延遲迴路電路設計 (Process-Resilient Fault-Tolerant DLL Design with Failure Monitor to Support Graceful Degradation)more

具有製程適應能力以及支援從容退化之線上失效監控技術之容錯型鎖延遲迴路電路設計 (Process-Resilient Fault-Tolerant DLL Design with Failure Monitor to Support Graceful Degradation)

經由新穎的... 極大極小時間數位轉換器達成快速地監控峰對峰值抖動 (Rapid Peak-to-Peak Jitter Monitoring by a Novel min-MAX Time-to-Digital Converter)more

經由新穎的極大極小時間數位轉換器達成快速地監控峰對峰值抖動 (Rapid Peak-to-Peak Jitter Monitoring by a Novel min-MAX Time-to-Digital Converter)

透過相位差... 監測系統對延遲鎖相迴路電路進行線上安全檢查 (Online Safety Checking for Delay Locked Loops via Phase Error Monitoring)more

透過相位差監測系統對延遲鎖相迴路電路進行線上安全檢查 (Online Safety Checking for Delay Locked Loops via Phase Error Monitoring)

使用多階類... 神經網路改進掃描鏈檢測準確率 (Improving Scan Chain Diagnostic Accuracy Using Multi-Stage Artificial Neural Networks)more

使用多階類神經網路改進掃描鏈檢測準確率 (Improving Scan Chain Diagnostic Accuracy Using Multi-Stage Artificial Neural Networks)

可用於超廣... 範圍延遲線的加速鎖定方案 (Accelerated Locking Scheme for Super-Wide Range Delay Line)more

可用於超廣範圍延遲線的加速鎖定方案 (Accelerated Locking Scheme for Super-Wide Range Delay Line)

一個使用乒... 乓型延遲線的高彈性 延遲鎖相迴路 (A highly resilient DLL using ping-pong delay line)more

一個使用乒乓型延遲線的高彈性 延遲鎖相迴路 (A highly resilient DLL using ping-pong delay line)

以鎖定延遲... 迴路為基礎的 多裸晶時脈訊號同步自動化方案 (Automatic DLL-Based Clock Synchronization Scheme for Multi-Die ICs)more

以鎖定延遲迴路為基礎的 多裸晶時脈訊號同步自動化方案 (Automatic DLL-Based Clock Synchronization Scheme for Multi-Die ICs)

使用監督式... 學習類神經網路於掃描鏈之檢測 (Scan Chain Diagnosis Using Supervised Artificial Neural Networks)more

使用監督式學習類神經網路於掃描鏈之檢測 (Scan Chain Diagnosis Using Supervised Artificial Neural Networks)

標準元件庫... 細胞為基礎的時間量化器之電路自動產生軟體 (Cell-based Time-to-Digital Converter Compiler)more

標準元件庫細胞為基礎的時間量化器之電路自動產生軟體 (Cell-based Time-to-Digital Converter Compiler)

晶片製程、... 電壓及溫度監測系統之建構及其數據分析 (Implementation of A Measurement System for PVT Monitoring of an IC and Its Data Analysis)more

晶片製程、電壓及溫度監測系統之建構及其數據分析 (Implementation of A Measurement System for PVT Monitoring of an IC and Its Data Analysis)

可容忍高度... 製程變異之全數位式的非整數型鎖相迴路之自動產生器軟體 (A Cell-Based Compiler for Process Resilient Fractional-N All-Digital PLLs)more

可容忍高度製程變異之全數位式的非整數型鎖相迴路之自動產生器軟體 (A Cell-Based Compiler for Process Resilient Fractional-N All-Digital PLLs)

物聯網晶片... 內之匹夫塔效應之雲端監測系統 (Cloud-Based PVTA Monitoring System for IoT Devices)more

物聯網晶片內之匹夫塔效應之雲端監測系統 (Cloud-Based PVTA Monitoring System for IoT Devices)

布線過後針... 對動態電源電壓降進行電源供應網路修補之辦法 (ECO Approach for Repairing Power Distribution Network to Mitigate Dynamic IR drop)more

布線過後針對動態電源電壓降進行電源供應網路修補之辦法 (ECO Approach for Repairing Power Distribution Network to Mitigate Dynamic IR drop)

應用於邏輯... 核心速度分級之寬頻時脈訊號產生方法 (A Wide-Range Clock Signal Generation Scheme for Speed Grading of a Logic Core)more

應用於邏輯核心速度分級之寬頻時脈訊號產生方法 (A Wide-Range Clock Signal Generation Scheme for Speed Grading of a Logic Core)

應用於SA... TA3.0 展頻時脈產生器 (Spread Spectrum Clock Generator for SATA3.0)more

應用於SATA3.0 展頻時脈產生器 (Spread Spectrum Clock Generator for SATA3.0)

一個易於製... 程轉換的並聯架構全細胞數位延遲鎖定迴路與自動產生器 (Parameterized Cell-Based All-Digital Delay-Locked-Loop (ADDLL) Architecture and Its Compiler to Support Easy Process Migration)more

一個易於製程轉換的並聯架構全細胞數位延遲鎖定迴路與自動產生器 (Parameterized Cell-Based All-Digital Delay-Locked-Loop (ADDLL) Architecture and Its Compiler to Support Easy Process Migration)

可補償溫度... 效應之三維晶片中電源電壓用穿矽連接孔的線上測試方法 (Temperature-Aware Online Testing of Power-Delivery TSVs in 3D-ICs)more

可補償溫度效應之三維晶片中電源電壓用穿矽連接孔的線上測試方法 (Temperature-Aware Online Testing of Power-Delivery TSVs in 3D-ICs)

應用於微小... 時脈網路延遲故障測試方法之可調式單一脈衝產生器 (Tunable One-Shot Pulse Generator for Testing of Small Clock Delay Fault)more

應用於微小時脈網路延遲故障測試方法之可調式單一脈衝產生器 (Tunable One-Shot Pulse Generator for Testing of Small Clock Delay Fault)

Onlin... e Slack-Time Binning for IO-Registered Die-to-Die Interconnects (用在具有輸入與輸出暫存器的裸晶連接線的線上寬裕時間分組方法)more

Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects (用在具有輸入與輸出暫存器的裸晶連接線的線上寬裕時間分組方法)

1-4GH... z鎖定延遲迴路為基底之 高速時脈訊號產生器 (1-4GHz DLL-Based High Speed Clock Generator)more

1-4GHz鎖定延遲迴路為基底之 高速時脈訊號產生器 (1-4GHz DLL-Based High Speed Clock Generator)

應用於脈衝... 雷達系統晶片之時序控制電路-具有溫度追蹤功能之可編程式寬可調區間相位偏移器 (A Programmable Wide-Range Phase Shifter with Temperature Tracking for the Timing Control of Pulsed Radar SoC)more

應用於脈衝雷達系統晶片之時序控制電路-具有溫度追蹤功能之可編程式寬可調區間相位偏移器 (A Programmable Wide-Range Phase Shifter with Temperature Tracking for the Timing Control of Pulsed Radar SoC)

三維晶片中... 之電源電壓用穿矽連接孔測試架構與方法 (Architecture and Method for Testing Power-Delivery TSVs in 3D-ICs)more

三維晶片中之電源電壓用穿矽連接孔測試架構與方法 (Architecture and Method for Testing Power-Delivery TSVs in 3D-ICs)

藉由可擴展... 的全局環結構達成各階段之穿矽連接孔的參數性故障測試 (A Scalable Global-Ring Based Architecture Supporting Parametric Fault Testing for Any-Bond TSVs)more

藉由可擴展的全局環結構達成各階段之穿矽連接孔的參數性故障測試 (A Scalable Global-Ring Based Architecture Supporting Parametric Fault Testing for Any-Bond TSVs)

可直接地檢... 測時脈網路之微小延遲故障的測試方法 (Explicit Testing of Small Clock Delay Fault)more

可直接地檢測時脈網路之微小延遲故障的測試方法 (Explicit Testing of Small Clock Delay Fault)

藉由分散式... 時間至數位碼轉換器監測長距離連接線的延遲時間 (Monitor the Delay of Long Interconnect via Distributed TDC)more

藉由分散式時間至數位碼轉換器監測長距離連接線的延遲時間 (Monitor the Delay of Long Interconnect via Distributed TDC)

三角積分鎖... 相迴路量化雜訊抑制相關技術 (Quantization Noise Suppression Techniques in Delta-Sigma Phase-Locked Loops)more

三角積分鎖相迴路量化雜訊抑制相關技術 (Quantization Noise Suppression Techniques in Delta-Sigma Phase-Locked Loops)

應用於脈衝... 雷達系統晶片之時序控制電路-可程式寬可調區間相位移動器 (A Programmable Wide-range Phase Shifter for the Timing Control of Pulsed Radar SoC)more

應用於脈衝雷達系統晶片之時序控制電路-可程式寬可調區間相位移動器 (A Programmable Wide-range Phase Shifter for the Timing Control of Pulsed Radar SoC)

適用於2.... 5維積體電路之中介層連接線的參數性故障測試和效能估測之研究 (Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wire in 2.5-D ICs)more

適用於2.5維積體電路之中介層連接線的參數性故障測試和效能估測之研究 (Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wire in 2.5-D ICs)

適用於2.... 5-D IC之中介層連接線時序感知測試和修復方法 (Timing aware testing and repair for interposer wires in 2.5-D IC)more

適用於2.5-D IC之中介層連接線時序感知測試和修復方法 (Timing aware testing and repair for interposer wires in 2.5-D IC)